Design and Implementation of Hybrid Multiplier Using ZFC

Abstract

The field of research has recently been driven to build systems with low power consumption and high speed due to the increasing number of portable devices. The rapid development of semiconductor technology has contributed to a growing need for portable and embedded digital signal processing (DSP) devices. All DSP applications, multipliers are essential components. For high speed DSP, low power, high speed multipliers are therefore required. All current commercial DSP processors have at least one dedicated multiplier unit since the capacity to compute at a quicker pace is necessary to achieve excellent performance in many DSP and graphic processing algorithms. Numerous researchers have developed a number of multipliers, including modified Booth multipliers, array, Booth, carry save, and Wallace tree. However, today’s computational circuits such as high performance processors, digital signal processing, and cryptographic algorithms require highly effective and speed multipliers. Hence, In this work, Design and Implementation of Hybrid Multiplier using ZFC (Zero Finding Logic) is presented. This Hybrid Multiplier is the combination of Finite Field Multiplier and Modified Kogee Stone Multiplier. The Zero Finding Logic is used to identify the zeros from the resultant product.