Adaptation in Optical Transport Networks with FPGA-Based GLDPC Decoding

Abstract

Since LDPC codes are well-known for their strong error correcting capabilities, this design intends to use them to make OTNs more adaptable and reliable. Because of the high-speed processing and adaptability offered by the FPGA implementation, it is possible to make real-time modifications to transmission conditions and data rates. In this research, we look examine how well the Generalized Low-Density Parity-Check (GLDPC) codes that have been suggested work on an FPGA platform. Three essential parts make up the FPGA system: a circuit for error counting, a GLDPC decoder, and a noise generator with a Gaussian distribution. To create white Gaussian noise samples, the Gaussian noise generator uses the Box-Muller algorithm in conjunction with two uniform generators based on Linear Feedback Shift Register (LFSR). Based on our findings, the proposed unified GLDPC decoder architecture is a practical option for next-gen high-speed fiber optical communications as it allows for variable net coding gains (NCGs) without an error floor at BER levels as low as 10-15.