1.
DRVKPYC. Design of 8 and 16 Bit LFSR with Maximum Length Feedback Polynomial & Its pipelined Structure Using Verilog HDL. IJRITCC [Internet]. 2014Nov.30 [cited 2025Dec.18];2(11):3337-9. Available from: https://www.ijritcc.org/index.php/ijritcc/article/view/3465