, S.Karpagambal, M.S.Thaen Malar,. “Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design”. International Journal on Recent and Innovation Trends in Computing and Communication 3, no. 2 (February 26, 2015): 529–533. Accessed December 9, 2025. https://www.ijritcc.org/index.php/ijritcc/article/view/3854.